A test system for electronic device testing can include a pin driver circuit that provides a voltage test pulse to a device under test (DUT). In response, the test system can be configured to measure a response from a DUT, such as to determine whether the DUT meets one or more specified operating parameters. A test system can optionally include multiple driver circuits, such as a class AB driver circuit and a class A driver circuit to provide circuit test signals having different amplitude or timing characteristics. In an example, the test system is configured to measure a response from a DUT using an active load and a comparator circuit to sense transitions at a DUT pin.
In an example, a system for testing digital integrated circuits (ICs) includes a driver circuit configured to provide multiple voltage levels (e.g., Vhigh, Vlow and Vterm) to a DUT. The DUT can exhibit bidirectional (I/O) capability in that it can both source and receive stimulus. The driver circuit's Vhigh and Vlow levels serve to stimulate a DUT while in its “input” state, and Vterm acts as a termination for the DUT in its “output” state. The process of switching between Vhigh, Vlow, and Vterm can be conceptualized as a collection of three switches, with one terminal of each switch connected to either Vhigh, Vlow, or Vterm, and the other terminal connected to a common 50 ohm resistor, which is then connected to the DUT node. In this way, transitions between the three levels can be realized by opening and closing the appropriate switches, such as with only one switch closed at any given time.
A feature of ATE test systems is an ability to deliver precisely timed Vhigh, Vlow, and Vterm signals or transitions to the DUT. It can be critical for a tester to provide substantially constant propagation delays for transitions between the three levels independent of temperature, frequency, duty cycle, pulse width or test vector history.
A problem with the switching system described above includes the so-called “first pulse problem” where a propagation delay of a given transition is influenced by the nature of previous transitions. This manifests as inconsistent, nonsystematic, or unpredictable propagation delay times. For example, transition times from Vhigh-to-Vlow, Vlow-to-Vhigh, Vhigh/low-to-Vterm and Vterm-to-Vhigh/Vlow can each be different, complicating test system calibration and implementation. Such transition time inconsistencies can limit system performance, for example by dictating a minimum driving signal pulse width or a minimum duration of the termination mode. As system or test operating speeds increase, these limitations can compromise efficacy of a test system.